實作

module top;

wire [3:0] x_in;

wire y_out;

system_clock #50 c1(x_in[0]);

system_clock #100 c2(x_in[1]);

system_clock #200 c3(x_in[2]);

system_clock #400 c4(x_in[3]);

and4_rt1 al(y_out,x_in);

endmodule

module number(e,a,b,c,d);

input a,b,c,d

output e;

wire a1,b1,c1,d1,w1,w2,w3,w4,w5;

not(a1,a);

not(b1,b);

not(c1,c);

not(d1,d);

and(w1,b,c1,d1);

and(w2,a,c1,d1);

and(w3,b,c,d);

and(w4,a,c,d);

and(w5,a1,b1,c,d1);

or(e,w1,w2,w3,w4,w5);

endmodule

module system_clock(clk);

parameter period=100;

output clk;

reg clk;

initial

clk=0;

always

begin

#(priod/2)clk=~clk;

end

always@(posedge clk)

if($time>10000)

$stop;

endmodule