作業2

module part1;

integer ia,ib;

reg a,b;

wire c;

xor x1(c,a,b);

initial

begin

for(ia=0;ia<=1ia++)

begin

a=ia;

for(ib=0;ib<=1;ib++)

begin

b=ib;
#10 $display("a=5d b=%d c=%d",a,b,c);

end

end

endendmodule

VIG硬體語言 AND 邏輯閘 n.1 work

module top;

wire a,b;

reg c;

system_clock #100 clock1(a);

system_clock #50 clock2(b);

always#1 c=a&b;

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initialclk=0;

alwaysbegin#(PERIOD/2)clk=~clk;

#(PERIOD-PERIOD/2)clk=~clk;

end

always@(posedge clk)

if ($time>1000)#(PERIOD-1)$stop;

endmodule