實作

module top;

wire [3:0] x_in;

wire y_out;

system_clock #50 c1(x_in[0]);

system_clock #100 c2(x_in[1]);

system_clock #200 c3(x_in[2]);

system_clock #400 c4(x_in[3]);

and4_rt1 al(y_out,x_in);

endmodule

module number(e,a,b,c,d);

input a,b,c,d

output e;

wire a1,b1,c1,d1,w1,w2,w3,w4,w5;

not(a1,a);

not(b1,b);

not(c1,c);

not(d1,d);

and(w1,b,c1,d1);

and(w2,a,c1,d1);

and(w3,b,c,d);

and(w4,a,c,d);

and(w5,a1,b1,c,d1);

or(e,w1,w2,w3,w4,w5);

endmodule

module system_clock(clk);

parameter period=100;

output clk;

reg clk;

initial

clk=0;

always

begin

#(priod/2)clk=~clk;

end

always@(posedge clk)

if($time>10000)

$stop;

endmodule

2009.11.16

module top;
wire [3:0]x_in;
system_clk #50 clkl(x_in[0]);
system_clk #100 clkl(x_in[1]);
system_clk #200 clkl(x_in[2]);
system_clk #400 clkl(x_in[3]);
and4_algo c1 (y_out,x_in);
endmodule


module and4_algo(y_out,x_in);
input[3:0] x_in;
output y_out;
reg y_out;
integer k;
always@(x_in)
begin:and_loop
y_out=1;
for(k=0;k<=3;k=k+1) if(x_in[k]==0) begin y_out=0; disable and_loop; end end endmodule module system_clk(clk); parameter period=100; output clk; reg clk; initial clk=0; always #(period/2)clk=~clk; always@(posedge clk) if($time>1000)
#(period-1)
$stop;
endmodule

比較器

module top();

wire A_lt_B,A_gt_B,A_eq_B;

wire [1:0]A,B;

system_clock #100 clock_1(A[0]);

system_clock #200 clock_2(A[1]);

system_clock #400 clock_3(B[0]);

system_clock #800 clock_4(B[1]);

compare_2c X1(A_lt_B,A_gt_B,A_eq_B,A,B);

endmodule

module compare_2c(A_lt_B,A_gt_B,A_eq_B,A,B);

input [1:0]A,B;

output A_lt_B,A_gt_B,A_eq_B;

reg A_lt_B,A_gt_B,A_eq_B;

always @(A or B)

begin

A_lt_B=0;

A_gt_B=0;

A_eq_B=0;

if (A==B)A_eq_B=1;

else if (A>B)A_gt_B=1;

end

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always begin#(PERIOD/2) clk=~clk ;#(PERIOD-PERIOD/2) clk=~clk ;end

always@(posedge clk)if($time>10000) #(PERIOD-1) $stop;

endmodule

作業2

module part1;

integer ia,ib;

reg a,b;

wire c;

xor x1(c,a,b);

initial

begin

for(ia=0;ia<=1ia++)

begin

a=ia;

for(ib=0;ib<=1;ib++)

begin

b=ib;
#10 $display("a=5d b=%d c=%d",a,b,c);

end

end

endendmodule

VIG硬體語言 AND 邏輯閘 n.1 work

module top;

wire a,b;

reg c;

system_clock #100 clock1(a);

system_clock #50 clock2(b);

always#1 c=a&b;

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initialclk=0;

alwaysbegin#(PERIOD/2)clk=~clk;

#(PERIOD-PERIOD/2)clk=~clk;

end

always@(posedge clk)

if ($time>1000)#(PERIOD-1)$stop;

endmodule